Semiconductor package

ABSTRACT

A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane between the leads and the die pad; a plurality of downset tie bars connecting the ground bar with the die pad; a plurality of ground wires bonding to both of the ground bar and the die pad; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of U.S. patent application Ser. No.12/273,559 filed Nov. 19, 2008, which is incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to packaging of semiconductors, and inparticular, to a leadframe semiconductor package.

2. Description of the Prior Art

Leadframe semiconductor packages are well known in the art. Aconventional leadframe typically includes a plurality of metal leadstemporarily held together in a planar arrangement about a central regionduring package manufacture by a rectangular frame. A die pad issupported in the central region by a plurality of tie bars that attachto the frame. The leads extend from a first end integral with the frameto an opposite second end adjacent to, but spaced apart from, the diepad.

During package manufacture, a semiconductor die is attached to the diepad. Wire-bonding pads on the die are then connected to selected ones ofthe inner ends of the leads by fine, conductive bonding wires to conveypower, ground or signals between the die and the leads. A protectivebody of an epoxy resin is molded over the assembly to enclose and sealthe die, the inner ends of the leads, and the wire bonds against harmfulenvironmental elements. The rectangular frame and the outer ends of theleads are left exposed outside of the body, and after molding, the frameis cut away from the leads and discarded, and the outer ends of theleads are appropriately formed for interconnection of the package withan external printed circuit board.

One known type of the leadframe semiconductor packages is the so-calledexposed die pad (E-pad) leadframe package that exposes the bottomsurface of the die pad to the outside of the encapsulation body. Theexposed die pad acts as a heat sink and can improve the heat-dissipationefficiency. Typically, the exposed die pad is electrically connected toa ground plane of the external printed circuit board.

It has been found that the E-pad leadframe package is subject to attacksof moisture. To avoid reliability problems due to moisture attacks anddelamination along the plastic body-metal interface, the ground wiresextended from the ground pads of the semiconductor die are not directlybonded onto the surface of the die pad, but instead the ground wires arebonded to a rectangular ring shaped ground bridge bar that encircles thedie pad at different downset planes. Typically, the ground bridge bar issupported by tie bars that connected with the die pad.

However, the prior art leadframe package with such ground bridge barconfiguration has a shortcoming of that the analog and digital groundwires randomly bonded together onto the ground bridge bar can result innoise or ground coupling, which is also known as water wave effects inTV systems. Another shortcoming is that the ground bridge bar isvulnerable to twist and deform, leading to poor bonding strength. It istherefore desirable to provide an improved leadframe package structurethat may eliminate the aforesaid digital and analog ground coupling andthe water wave effects in TV systems.

SUMMARY OF THE INVENTION

It is one objective of this invention to provide an improvedsemiconductor package structure with improved performance and reducedground coupling.

To these ends, according to one aspect of the present invention, thereis provided a semiconductor package including a die pad; a semiconductordie mounted on the die pad; a plurality of leads in a first horizontalplane disposed along peripheral edges of the die pad; a ground bardownset from the first horizontal plane to a second horizontal planebetween the leads and the die pad; a plurality of downset tie barsconnecting the ground bar with the die pad; a plurality of ground wiresbonding to both of the ground bar and the die pad; and a moldingcompound at least partially encapsulating the die pad, inner ends of theleads such that bottom surface of the die pad is exposed within themolding compound.

In one aspect, a semiconductor package includes a die pad; asemiconductor die mounted on the die pad; a plurality of leads in afirst horizontal plane disposed along peripheral edges of the die pad; afirst ground bar downset from the first horizontal plane to a secondhorizontal plane; a second ground bar flush with the leads; a firstdownset tie bar connecting the first ground bar to the die pad; a seconddownset tie bar connecting the second ground bar with the first groundbar; a plurality of first ground wires for conveying digital groundbonding to the first ground bar; a plurality of second ground wires forconveying analog ground bonding to the second ground bar; and a moldingcompound at least partially encapsulating the die pad, inner ends of theleads such that bottom surface of the die pad is exposed within themolding compound.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings:

FIG. 1 is a top view of a semiconductor package according to oneembodiment of the present invention;

FIG. 2 is a schematic, cross-sectional view of the semiconductor packageof FIG. 1;

FIG. 3 shows some examples of the separated ground bar segmentsaccording to this invention;

FIG. 4 is a schematic, cross-sectional view of a semiconductor packagein accordance with another embodiment of this invention; and

FIG. 5 is a partial plan view of the semiconductor package in FIG. 4.

DETAILED DESCRIPTION

The technology trend in the consumer electronics can be summarized asmore functionalities in a smaller geometry with low cost. The exposedpad low-profile quad flat package (E-pad LQFP) is a low cost solutionfor multimedia chips, but its disadvantages are limited pin count andworse electrical characteristics.

As previously mentioned, one problem relates to delamination of theleadframe components from the plastic package body, and the attendantproblem of penetration of the package by moisture. In particular, thevarious parts of a semiconductor package experience greatly differentamounts of thermal expansion and contraction with temperature changesdue to the relatively large differences in the coefficients of thermalexpansion of their respective materials, e.g., metal, epoxy resin, andsilicon. As a result, the leadframe components can become delaminatedfrom the package body with temperature cycling of the package duringmanufacture or operation.

Where delamination occurs at a boundary of the package body, amicroscopic crack is created for the penetration of the package bymoisture. The moisture can corrode metallization present in its path,resulting in subsequent current leakage through the corrosive path. Toavoid reliability problems due to moisture attacks and delamination, theground wires are typically not bonded onto the surface of the die pad.Instead, the ground wires, either digital ground wires or analog groundwires, are bonded to a ground bridge bar that encircles the die pad atdifferent downset planes. However, such configuration results in groundsignal coupling noise. The present invention addresses this problem.

One or more implementations of the present invention will now bedescribed with reference to the attached drawings, wherein likereference numerals are used to refer to like elements throughout, andwherein the illustrated structures are not necessarily drawn to scale.

FIG. 1 is a top view of a semiconductor package according to oneembodiment of the present invention. FIG. 2 is a schematic,cross-sectional view of the semiconductor package of FIG. 1. As shown inFIG. 1 and FIG. 2, according to the first embodiment of this invention,a semiconductor package 10 comprises a semiconductor die 20 mounted ontothe first surface 110 a of a die pad 110, a plurality of leads 120 in afirst horizontal plane disposed along the peripheral edges of the diepad 110, a ground bar 130 downset from the first horizontal plane to asecond horizontal plane between inner ends 120 a of the leads 120 andthe die pad 110, four connecting bars 142 extending outward from fourcorners of the die pad 110, and a plurality of downset tie bars 144connecting the ground bar 130 with the die pad 110. A molding compound30 at least partially encapsulates the die pad 110, the inner ends 120 aof the leads 120 such that the bottom surface 110 b of the die pad 110is exposed within the molding compound 30.

According to this embodiment, a peripheral groove 112 is etched into thefirst surface 110 a of the die pad 110 and is disposed around thesemiconductor die 20. A plating layer 114 such as silver or noble metalsmay be formed within the peripheral groove 112 for wire bondingpurposes. The peripheral groove 112 can increase the coupling strength.To securely lock the leadframe components to the plastic body of thepackage, thereby effectively reducing both the amount of delamination ofthe leadframe from the body and the resulting penetration of the body bymoisture, the bottom surface 110 b of the die pad 110 may be partiallyetched along the periphery of the die pad 110 to form a step 116.

The semiconductor die 20 comprises a plurality of bonding pads 202 onits active surface 20 a. The bonding pads 202 further comprise aplurality of first ground pads 202 a and a plurality of second groundpads 202 b. According to this embodiment, the plurality of first groundpads 202 a are sensitive analog ground pads, while the plurality ofsecond ground pads 202 b are digital ground pads. In another embodiment,the plurality of first ground pads 202 a are digital ground pads, whilethe plurality of second ground pads 202 b are sensitive analog groundpads.

A plurality of first bonding wires 212 are provided to connect therespective first ground pads 202 a to the ground bar 130. A plurality ofsecond bonding wires 214 are provided to connect the respective secondground pads 202 b to the plated top surface of the peripheral groove112. A plurality of third bonding wires 216 are provided to connect thebond pads 202 c such as signal or power pads to the leads 120. Accordingto this embodiment, a plurality of fourth bonding wires 218 are providedto connect the die pad 110 with the ground bar 130 in order to reducethe ground inductance. By separating the digital ground path from theanalog ground path, the sensitive analog ground signal is not interferedby the digital ground signal during operation and the water wave effectcan be eliminated.

The ground bar 130 may have a continuous ring shape. However, thepresent invention is not limited thereto. Discontinuities 132 may beprovided in the ground bar 130, thereby forming separated ground barsegments 130 a and 130 b. Each of the ground bar segments 130 a and 130b are supported by respective tie bars 144. A plurality of fifth bondingwires 220 are provided to connect the second ground pads 202 b to theground bar segment 130 b. A plurality of sixth bonding wires 222 areprovided to connect the first ground pads 202 a to the ground barsegment 130 a. Since the digital ground path is separated from theanalog ground path by wire bonding to separate ground bar segments 130 aand 130 b, the sensitive analog ground signal is not interfered by thedigital ground signal.

The separated ground bar segments may have various shapes, for example,T shape, U shape, Π shape, L shape, serpentine shape or irregularshapes. FIG. 3 shows some examples of the separated ground bar segmentsaccording to this invention. It is one germane feature of the presentinvention that the bonding wires for conveying digital ground signal areboned to one of the separated ground bar segments, while the bondingwires for conveying analog ground signal are bonded to the other. Indoing so, the interference between the digital ground and the analogground is avoided.

FIG. 4 is a schematic, cross-sectional view of a semiconductor package10 a in accordance with another embodiment of this invention. FIG. 5 isa partial plan view of the semiconductor package in FIG. 4. As shown inFIG. 4 and FIG. 5, likewise, the semiconductor package 10 a comprises asemiconductor die 20 mounted onto the first surface 110 a of a die pad110, a plurality of leads 120 in a first horizontal plane disposed alongthe peripheral edges of the die pad 110, a ground bar 320 downset fromthe first horizontal plane to a second horizontal plane between innerends 120 a of the leads 120 and the die pad 110, and a plurality ofdownset tie bars 144 a connecting the ground bar 320 with the die pad110.

An extended ground bar 330 that is flush with the plurality of leads 120in the first horizontal plane is provided between the inner ends 120 aof the leads 120 and the ground bar 320. The extended ground bar 330 issupported by the downset tie bar 144 b that connects to the ground bar320. A molding compound 30 at least partially encapsulates the die pad110, the inner ends 120 a of the leads 120 such that the bottom surface110 b of the die pad 110 is exposed within the molding compound 30.

To securely lock the leadframe components to the plastic body of thepackage, thereby effectively reducing both the amount of delamination ofthe leadframe from the body and the resulting penetration of the body bymoisture, the bottom surface 110 b of the die pad 110 may be partiallyetched along the periphery of the die pad 110 to form a step 116. Inaddition, a peripheral groove may be etched into the first surface 110 aof the die pad 110 to improve the interlock between the molding compound30 and the die pad 110.

The semiconductor die 20 comprises a plurality of bonding pads 202 onits active surface 20 a. The bonding pads 202 further comprise aplurality of first ground pads 202 a and a plurality of second groundpads 202 b. According to this embodiment, the plurality of first groundpads 202 a are digital ground pads, while the plurality of second groundpads 202 b are sensitive analog ground pads. A plurality of firstbonding wires 312 are provided to connect the respective first groundpads 202 a to the ground bar 320. A plurality of second bonding wires314 are provided to connect the respective second ground pads 202 b tothe extended ground bar 330. A plurality of third bonding wires 316 areprovided to connect the bond pads 202 c such as signal or power pads tothe leads 120. Optionally, a plurality of fourth bonding wires 318 areprovided to connect the die pad 110 with the die 20. By separating thedigital ground path from the analog ground path, the sensitive analogground signal is not interfered by the digital ground signal duringoperation and the water wave effect can be eliminated.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A semiconductor package, comprising: a die pad; a semiconductor diemounted on the die pad; a plurality of leads in a first horizontal planedisposed along peripheral edges of the die pad; a ground bar downsetfrom the first horizontal plane to a second horizontal plane between theleads and the die pad; a plurality of downset tie bars connecting theground bar with the die pad; a set of first ground wires directlyelectrically connected to the semiconductor die and the ground bar; aset of second ground wires directly electrically connected to thesemiconductor die and the die pad; a molding compound at least partiallyencapsulating the die pad, inner ends of the leads such that bottomsurface of the die pad is exposed within the molding compound; aplurality of signal wires provided to connect signal pads on thesemiconductor die to the leads; and a plurality of power wires providedto connect power pads on the semiconductor die to the leads.
 2. Thesemiconductor package according to claim 1 wherein the first groundwires are analog ground and the second ground wires are digital ground.3. The semiconductor package according to claim 2 wherein the firstground wires are directly bonded to the ground bar and the second groundwires are directly bonded to the die pad.
 4. The semiconductor packageaccording to claim 3 wherein the second ground wires are bonded to aperipheral groove partially etched into the die pad.
 5. Thesemiconductor package according to claim 2 wherein the first and secondground wires are all bonded to the ground bar, and wherein at least onediscontinuity is provided in the ground bar to separate the first groundwires from the second ground wires.
 6. The semiconductor packageaccording to claim 1 wherein the ground bar has T shape, U shape, Πshape, L shape, serpentine shape or irregular shapes.
 7. Thesemiconductor package according to claim 1 wherein a plurality ofbonding wires extend between the die pad and the ground bar.
 8. Asemiconductor package, comprising: a die pad; a semiconductor diemounted on the die pad; a plurality of leads in a first horizontal planedisposed along peripheral edges of the die pad; a first ground bardownset from the first horizontal plane to a second horizontal plane; asecond ground bar flush with and separated from the leads; a firstdownset tie bar connecting the first ground bar to the die pad; a seconddownset tie bar connecting the second ground bar with the first groundbar; a plurality of first ground wires for conveying digital grounddirectly and electrically connected to the first ground bar; a pluralityof second ground wires for conveying analog ground directly andelectrically connected to the second ground bar; and a molding compoundat least partially encapsulating the die pad, inner ends of the leadssuch that bottom surface of the die pad is exposed within the moldingcompound; wherein a plurality of third bonding wires are provided toconnect signal or power pads to the leads and a plurality of thirdbonding wires are provided to connect signal or power pads to the leads.9. The semiconductor package according to claim 8 wherein a plurality offourth bonding wires are provided to connect the semiconductor die withthe die pad.